TC59LM905AMB Datasheet | Toshiba

RIPTION Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM913/05AMB is Network FCRAMTM containing 536,870,912 memory cells. TC59LM913AMB is organized as 8,388,608-words × 4 banks × 16 bits, TC59LM905AMB is organized as 16,777,216-words × 4 banks × 8 bits. TC59LM913/05AMB feature a fully synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. TC59LM913/05AMB can operate fast core cycle pared with regular DDR SDRAM. TC59LM913/05AMB is suitable for Network, Server and other applications where large memory density and low power consumption are required. The Output Driver for Network FCRAMTM is capable of high quality fast data transfer under light loading condition. Features PARAMETER t CK t RC t RAC Clock Cycle Time (min) CL = 3 CL = 4 -50 5.5 ns 5.0 ns 25.0 ns 22.0 ns TBD TBD TBD TC59LM913/05 -55 6.0 ns 5.5 ns 27.5 ns 24.0 ns TBD TBD TBD -60 6.5 ns 6.0 ns 30.0 ns 26.0 ns TBD TBD TBD Random Read/Write Cycle Time (min) Random Access Time (max) IDD1S Operating Current (single bank) (max) l DD2P Power Down Current (max) l DD6 Self-Refresh Current (max) - - - - - - - - - - - - - Fully Synchronous Operation - Double Data Rate (DDR) Data input/output are synchronized with both edges of DQS. - Differential Clock (CLK and CLK ) inputs CS , FN and all address input signals are sampled on the positive edge of CLK. Output data (DQs and DQS) is aligned to the crossings of CLK and CLK . Fast clock cycle time of 5 ns minimum Clock: 200 MHz maximum Data: 400 Mbps/pin maximum Fast cycle and Short Latency Distributed Auto-Refresh cycle in 7.8 µs Self-Refresh Power Down Mode Variable Write Length Control Write Latency = CAS Latency-1 Programable CAS Latency and Burst Length CAS Latency = 3, 4 Burst Length = 2, 4 Organization: TC59LM813AMB : 8,388,608 words × 4 banks × 16 bits TC59LM805AMB : 16,777,216 words × 4 banks × 8 bits Power Supply...